1. General information about the module
Module code: SEM10129
Vietnamese module designation: THIẾT KẾ LÕI IP
English module designation: Intellectual property (IP) core design
Credit points: 3
Workload:
- Contact Hours: Lectures, lesson: 30 hours (in class)
- Lab works, project, seminar: 30 hours
- Exercise:
- Private study: 90 hours
Type of module: Specialization
Required and recommended prerequisites for joining the module: None
Modules taken before this module: None
2. Module objectives/intended learning outcomes
This course provides students with knowledge and practical skills in the analysis and design of Intellectual Property (IP) cores on FPGA platforms. Students will gain an understanding of the theoretical foundations of IP core design and the top-down design methodology commonly applied to IP development.
The course also enables students to understand and apply the process of developing a complete IP core, from hardware implementation to software development. Students will design IP cores using Qsys to implement basic I/O functions and custom I/O interfaces using the Verilog hardware description language (HDL).
Students will also develop C programs using the Nios II Embedded Development Suite (Nios II EDS) to control I/O interfaces. In addition, they will design hardware systems in Qsys to interface with memory, timers, DMA controllers, and other peripherals.