Synopsys is pleased to announce its recruitment drive for February 2025 as part of our expansion plans to grow our team in Ho Chi Minh City, Hanoi, and Da Nang. We are currently looking for talented candidates for both internship and entry-level positions, targeting final-year students and recent graduates (0-2 years of experience). Please review the detailed information below:
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INTERNSHIP POSITION |
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Position |
Location |
JD link |
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CAD R&D Engineering Intern |
Đa Nang/ HCM City (Tan Binh) |
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ENTRY LEVEL POSITION |
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Position |
Location |
JD link |
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Memory Circuit Design Engineer (R&D Engineering) |
Ha Noi |
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Analog Circuit Design Engineer |
Ha Noi |
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Đa Nang |
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HCM City (Tan Binh) |
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Top-level Analog Layout Design Engineer |
Đa Nang |
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SoC Subsystem RTL Integration Engineer |
HCM City (District 7) |
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General Requirements
+ Educational Background: Bachelor’s or Master’s degree in fields such as Electronics & Telecommunications, Electrical Engineering, Mechatronics, Automation, Computer Science, Embedded Systems, Industrial Informatics, Physics, or related disciplines.
+ For Entry-Level Positions: Candidates should have graduated or expect to graduate in early 2025.
+ For Internship Positions: Final-year students who are expected to graduate in 2025.
+ GPA Requirement: Minimum 3.0/4 or 7.0/10.
+ Familiarity with IC Design or related concepts.
+ Internship experience in semiconductor or chip design companies is a plus.
+ Participation in IC design training courses or related research experience is an advantage.
+ Proficiency in English (all four skills).
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How to Apply
+ Application Materials: CV (in English) and academic transcript (combined into a single PDF file).
+ Submission: Apply directly via the JD link provided for each position.
+ For any inquiries, please get in touch with the Talent Acquisition Team at vn-staffing@synopsys.com.